Fuelled by exponential increases in device clock speeds, the heat which must be dissipated in electronic devices has grown dramatically in recent years. Poor heat dissipation in packaged electronic devices limits device performance and the size of the module. In some cases, the need for an external heat sink to manage the thermal dissipation has limited the size of a small module or end-product which is not in tune with the key technology trend. Electronics gadgets are growing smaller in size so that ever smaller modules containing an ever increasing density of devices are desired.
Heat dissipation is an increasing problem and improved thermal management is required. To date, this problem has not been satisfactorily solved to a extent particularly for simple low-cost heat dissipation.
One solution is the cavity-down approach. However, the routing space for signals, powers and grounds traces is limited which results in lower I/Os. Also, the assembly processes are difficult with high material and packaging costs.
U.S. Pat. No. 6,339,254B1 is said to disclose a stacked multi-chip assembly including a plurality of integrated circuit die directly attached to a substrate having pads corresponding to terminals on the die and interconnections between the die, and also external contacts.
U.S. Pat. No. 5,681,663 is said to disclose a heat spreader carrier strip including a first strip of laminated material portioned into smaller heat spreader portions with a welded second strip. Thermal manufacturing cycles are said not to cause a bowing of the second strip or of the heat spreader sections.
U.S. Pat. No. 5,156,923 is said to disclose a heat transferring circuit substrate including layers of copper and Invar which have limited thermal expansion.
U.S. Pat. No. 5,358,795 is said to disclose a heat-conductive material which receives and releases heat evenly, has high thermal conductivity, and can have any desired thermal expansion coefficient.
U.S. Pat. No. 5,736,785 is said to disclose a structure, shown in FIG. 5a, where a planar heat spreader is mounted on the top surface of a semiconductor die, which in turn is mounted on and electrically connected to a substrate. The planar heat spreader comprises a central recessed portion protruding from the bottom surface of the heat spreader surrounded by a plurality of apertures at the edges. The die is coated with a layer of adhesive covering also the bonding wires attaching the die to the substrate. This structure has a limited thermal efficiency.